GitHub

Hardware-accelerated SHA-256 implemented on a PYNQ-Z2 FPGA. Includes custom SystemVerilog IP, AXI4-Lite/DMA integration, and Python/Jupyter interface. Achieves faster hashing ...

This repository contains the full implementation and documentation of a hardware-accelerated SHA-256 hashing engine developed as a final university project. The project leverages the Xilinx PYNQ-Z2 ...
IEEE

SHA-256 Hash Generator in Verilog HDL

Abstract: An implementation of SHA-256 hash generator is presented. A block has been described in Verilog HDL. A generator code is written with basic logical and arithmetic operations to create a ...