No matter what, system architects are always going to have to contend with one – and possibly more – bottlenecks when they design the machines that store and crunch the data that makes the world go ...

This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining that performance is ...

During the past two years, a great deal of speculation has swirled around the direction VME architecture development should take. Although newer standards, such as CompactPCI and industrial-grade ...

Anyone who’s bought or researched buying a new SSD for their PC understands their limitations: they’re often constrained by the PCI Express bus to the rest of the PC, and they generate tons of heat.

If the datacenter had been taken over by InfiniBand, as was originally intended back in the late 1990s, then PCI-Express peripheral buses and certainly PCI-Express switching – and maybe even Ethernet ...

PCI Express (PCIe) is the fastest interface available to facilitate PC/FPGA communications. FPGA vendors have offered PCIe cores to harness this power for some time, but the cores are too rudimentary ...

The new E-761 controls 3 logical axes of closed-loop piezoelectric nanopositioning systems and is designed to provide more flexibility and better overall value than any other digital piezo controller ...

Designed for flexible integration of applications where the PCI or PCMCIA bus and HDLC/SDLC or asynchronous communications are required, the ACB-MP.PCI (PCI bus) and PC-ACB-MP (PCMCIA) single-port, ...

For more than a decade the PCI bus has been the backbone of personal computers. Other systems, such as telephony and networking, adopted the technology for its cost and performance advantages. But now ...