Electronic Design

Implement Abstraction By Encapsulation In SystemC

High-level design (HLD) represents a hardware design at a more abstract level than register transfer level (RTL). A high-level synthesis (HLS) tool then can be used to produce the RTL necessary to ...
Design-Reuse

SystemC library supporting OVM compliant verification methodology

This paper describes the SystemC library that support Open Verification Methodology as defined by Mentor Graphics and Cadence with their SystemVerilog–based approach. Application of the library in ...
EDN

SystemC 2.1 moving closer to IEEE standardization

ANAHEIM, Calif. — The Open SystemC Initiative (OSCI), an independent organization dedicated to supporting and advancing SystemC as an industry standard language for electronic system-level design, ...
EDN

SystemC fitted for verification duties

SAN JOSE, Calif. — In a push to establish a new design verification standard, the Open SystemC Initiative last week announced the SystemC Verification standard, based on Cadence Design Systems Inc.'s ...
Design-Reuse

Accelerating High-Level SysML and SystemC SoC Designs

SysML, the dedicated system level UML-based notation proposed by the OMG, is gaining a lot of momentum as a system level design standard. Design productivity is one of the main challenges facing the ...
Semiconductor Engineering

Is SystemC Broken?

In order to perform architectural exploration, performance analysis and optimization, early validation of software, improved productivity in hardware development and many other tasks, the industry ...