System architects working on system-on-chip (SoC) designs are hampered by the dearth of reliable ways to evaluate an architecture or verify hardware and software together. Fortunately, SystemC, an ...

As system-on-chip complexity grows, designers are turning to electronic system-level (ESL) methodologies to create next-generation designs. Designers might hesitate to use ESL because of legacy RTL ...

The use of IP (intellectual property) as basic building blocks is an established practice for SoC designs. Most IP is developed without chip-level context and very little knowledge about physical ...

June 14, 2017 -- Mentor, a Siemens business, has further expanded its Mentor Safe functional safety assurance program by qualifying the ISO 26262 compliance of documentation for its Oasys-RTL Physical ...

Experts at the Table, part one: Where the holes are showing up in tools and flows for advanced designs. Not all vendors or tools play nicely together, and no one really knows what’s going to happen ...

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...

Before a chip design is turned from a hardware design language (HDL) like VHDL or Verilog into physical hardware, testing and validating the design is an essential step. Yet simulating a HDL design is ...

The standard approach for testing IC logic is the use of scan chains, with embedded compression as the standard approach for applying scan patterns. Embedded compression enables the same test quality ...