EDN

RTL coding architecture affects power estimation & analysis

A well thought out design flow for SoCs ensures that the resulting device meets the requirement of low power dissipation. To meet these goals at the device level, individual modules (or components of ...
Electronic Design

Functional Analyzer Scopes Out SoC Defects In RTL

Expanding predictive analysis technology into the functional space, the Periscope functional analysis tool helps engineers quickly determine whether their RTL design descriptions are functionally ...
Semiconductor Engineering

Micro-Architectural Exploration For Low Power Design

The adoption of finFET technology has created a tectonic shift in the chip design landscape. In addition to better performance (within the same power envelope) and higher reliability, finFETs have ...
EDN

Design of FIFO based Interface Communicator[ ASIC design ]

1)Programming Languages: Verilog HDL, VHDL, C, C++, TCL scripting, HTML 2)Operating Systems: Windows, Unix and Mac operating systems 3)EDA Tools: Cadence - Virtuoso ...