Dallas, Tex.— Texas Instruments Inc.'s PCI Express (PCIe) x1 physical layer (PHY) chip has hit the market in volume, providing a low-cost PCI Express endpoint device for a wide variety of sectors such ...

SUNNYVALE, Calif. --Nov. 2, 2009--MoSys, Inc., a leading supplier of differentiated high density embedded memory and high data rate parallel and serial interface IP, today announced the availability ...

The PX1011B is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The PX1011B PCI Express PHY is ...

The GL9711 GigaCourier from Genesys Logic provides a 125-MHz 16-bit or 250-MHz 8-bit PIPE (PHY interface for PCI Express) interface to tie into the host system logic. This chip also offers a ...

SAN FRANCISCO, CA - June 7, 2004 - TriCN, a leading developer of intellectual property (IP) for high-speed semiconductor interface technology, today announced the immediate availability of the most ...

Integrated and optimized PHY and digital controller solution enables high-bandwidth and low-latency connectivity for next-generation applications in artificial intelligence (AI), data center, ...

MOUNTAIN VIEW, USA: Synopsys Inc. announced the availability of the DesignWare PHY IP for PCI Express 2.0 (Gen II), based on the PCI Express 2.0 base specification. This product release further ...

Delivers data rate of up to 64 GT/s for high-performance workloads Supports the full feature set of PCIe 6.0 with PHY support for CXL 3.0 Offers complete IP solution optimized for latency, power, and ...

Rambus has just announced the availability of its next-gen PCIe 6.0 Interface Subsystem that packs PHY and controller IP, with the latest version of the Compute Express Link (CXL) specification ...

PCI Express (PCIe) architecture is the ubiquitous Load/Store IO technology. Nonetheless, a host of myths and misunderstandings hold numerous engineers back from applying PCIe technology as broadly and ...