This is very simple and useful project which gives an idea about how to build the simple logic gates i.e. AND, OR & NOT gates using one of the universal gates – NAND Gate. This is very simple and ...

Applications of commercially available integrated timers, including the NE/SE555, are fairly limited when used in their monostable mode. This is due to their inability to function with all types of ...

Density and speed of IC’s have increased exponentially for several decades, following a trend described by Moore’s Law. While it is accepted that this exponential improvement trend will end, it is ...

This is going to be a column that’s divided into three sections. It’s based on a question that a student posed in the EEWeb forums, and he also sent it directly to yours truly. The core of this ...

Micron Technology recently unveiled 176-layer, triple-level-cell (TLC), 3D NAND flash memory with a 30% smaller die size that employs a new replacement-gate (RG) NAND technology. The chips offer a 35% ...

Rob Crooke, the Vice President and General Manager of the NVM (Non-Volatile Memory) Solutions Group at Intel, announced the impending release of 3D NAND at Intel's Investor Meeting. Incidentally, the ...

Intel-Micron have recently introduced a scalable planar NAND cell for the 20nm technology [1]. Replacement of conventional wrap floating gate (FG) NAND memory cell with a High-K/Metal gate planar cell ...