EDN

Do we need a new FPGA structure for prototyping?

I have been talking to a lot of people recently about the subject of prototyping. Not only do I believe that it is one of the most important applications related to the success of ESL, but to the ...
EDN

FPGA adaptability combines with ASIC routing structure

Achronix Semiconductor Corp. claims that its Speedster7t family of FPGAs designed for artificial intelligence (AI), machine learning (ML), and other high-bandwidth workloads offers ASIC-like ...
GIGAZINE

What is the content of the 'FPGA' that can change the circuit structure adopted by Microsoft and Amazon?

The first FPGA 'XC2064' developed by Xilinx in 1985 was said to have a much simpler structure than modern FPGAs. Nowadays, FPGAs can be programmed in standardized languages such as Verilog, but at ...
Design-Reuse

Tier Logic announces innovative 3D-FPGA technology: low-cost FPGAs & no-risk, timing-exact ASICs

Santa Clara, Calif., March 10, 2010. Tier Logic, Inc., a privately held fabless semiconductor company, today introduced its new 3D-based technology for FPGAs and ASICs, known respectively as its ...
Comics Gaming Magazine on MSN

SuperStation One review

The SuperStation One, courtesy of Taki Udon and Retro Remake, is a PlayStation One (second-generation PSX) inspired MiSTer ...
Design-Reuse

Prototyping Mesh-of-Tree NOC Based MPSOC on Mesh-of-Tree FPGA Devices

Multi-Processors System on Chip (MPSoC) is a growing industry; studies predict the use of hundreds of processors in one system, however the impact of targeted device internal structure on the ...
Electronics Weekly

Asynchronous FPGA clocks at 1.5GHz

Californian start-up Achronix has revealed details of its 1.5GHz asynchronous FPGA, which includes 10.3Gbit/s serialiser/deserialisers (serdes). “We get our speed from the underlying silicon ...
Electronic Design

FPGAs Enter The Third Dimension

Tabula’s ABAX chips take FPGA design to the next level. They implement a virtual 3D architecture by dynamically changing the underlying FPGA definition on each clock cycle. Accomplishing this feat ...
Semiconductor Engineering

Prototyping Partitioning Problems

Gaps are widening in the prototyping of large, complex chips because the speed and capacity of the FPGA is not keeping pace with rapid rollout pace of advanced ASICs. This is a new twist for a ...
Semiconductor Engineering

The Rise and Fall of Synthesis Bugs in Safety-Critical FPGAs

How to create an implementation signoff flow proving that the final FPGA netlist is functionally equivalent to the RTL model. For standards IEC 61508 / ISO 26262 / EN 50128 / DO-254. FPGAs are the ...