Of all the electronic design automation (EDA) tools on the market, design for test (DFT) may be the most under-appreciated; even though building testability into a chip during the design phase will ...

As the demand for processing power for artificial intelligence (AI) applications grows, semiconductor companies are racing to develop AI-specific silicon. The AI market is incredibly dynamic, with ...

As the name suggests, electronic design automation (EDA) companies strive to provide as much automation as possible to simplify the design process. However, many companies develop customized flows ...

Shipping high-quality ICs requires that design-for-test (DFT) methodologies be included in a design. DFT provides external access at the device’s I/O pins to internal registers to either control or ...

SUNNYVALE, Calif., June 9, 2020 — Real Intent, Inc., today announced Verix DFT, a full-chip, multimode DFT static sign-off tool. Verix DFT’s comprehensive set of fine-grained DFT rules help designers ...

This paper describes how using a smarter DFT infrastructure and automation can greatly improve the DFT schedule. A structural DFT infrastructure based on plug-and-play principles is used to enable ...

The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, ...

It is often said that the emergence of the System-on-Chip will require fundamental changes in the approaches to design for testability (DFT.) These changes, it has been suggested, will take the form ...

With any new SoC project, there are more things to go wrong than ever imagined during the optimistic early phase of defining the product, writes Ron Press, of Mentor, a Siemens Business. However, the ...

Bus-based scan data distribution architecture enables true bottom-up DFT flows, writes Geir Eide of Siemens Digital Industries Software. The dramatic rise in manufacturing test time for today’s large ...