EDN

Aldec releases Active-HDL 7.1

Well known for its mixed-language simulation and advanced design tools for ASIC and FPGA devices, Aldec, Inc., has announced the release of Active-HDL 7.1. Active-HDL 7.1 is an FPGA and ASIC design ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
EDN

Aldec’s Active-HDL 7.1 adds new simulation technology

SAN FRANCISCO — Aldec Inc. has released a new version of its Active-HDL 7.1 FPGA and ASIC design entry and verification platform, including several new tools. Aldec (Henderson, Nev.) said new tools ...
Electronic Design

Graphical Code Coverage Tool Speeds Design Debugging

Code Snooper, a code coverage software tool for use with the Active-HDL design and verification environment is integrated with the Active-HDL simulation kernel and does not require additional ...
Design-Reuse

Aldec delivers Global Project Management for Complex FPGA Designs with the latest release of Active-HDL

Henderson, NV – October 23, 2013 – Aldec, Inc., today announced the immediate availability of Active-HDL™ version 9.3, introducing a revolutionary approach to the increasing challenges of global ...