The adder looks complicated, but it really is just a half-adder and full-adder piped together in exactly the same way it would be wired up with CMOS or TTL gates. The video below shows it in action.

This paper contributes to a better knowledge of the behavior of conventional CMOS and CPL full-adder circuit when low voltage, less delay, low power or small power delay products are of concern.

In this paper, the authors present a design of Full Adder circuit using AVL techniques for low power operation. The approach for the design is based on XOR/XNOR & Transmission gate for single bit ...

A technical paper titled “Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET)” was published by researchers at Konkuk University, Korea National ...

--MicroAlgo Inc., today announced the successful development of a groundbreaking quantum algorithm technology, specifically a FULL adder operation based on CPU registers in quantum gate computers ...